The invention relates to a method for fabricating a semiconductor memory device, and more particularly, to a method for fabricating a column control block of the semiconductor memory device.
Most semiconductor memory devices such as Dynamic Random Access Memory (DRAM) devices employ a hierarchical data bus structure. That is, a local data bus is arranged in a bank region and a global data bus is arranged in a peripheral region. The local data bus itself may be hierarchically disposed.
FIG. 1 illustrates a data bus structure of a DRAM device.
Referring to FIG. 1, a bank includes a plurality of cell arrays formed in a matrix shape. First to fourth segment data buses SIO<0>, SIO<1>, SIO<2>, and SIO<3> are arranged in a row direction in the cell array. First to sixteenth local data buses LIO 0 to LIO 15 are arranged in a column direction perpendicular to the first to fourth segment data buses SIO<0>, SIO<1>, SIO<2>, and SIO<3>. Generally, the first to fourth segment data buses SIO<0>, SIO<1>, SIO<2>, and SIO<3> and the first to sixteenth local data buses LIO 0 to LIO 15 are embodied in differential lines.
Although not shown in this figure, first to sixteenth global data buses GIO 0 to GIO 15 are arranged in a row direction in the peripheral region under the bank. A column control block is arranged between the memory cell array and the first to sixteenth global data buses GIO 0 to GIO 15. The column control block includes a write driver WD and a data bus sensing amplifier IOSA.
FIG. 2A illustrates a data transmission path for a read operation of the DRAM device.
Referring to FIG. 2A, when the DRAM device performs the read operation, the data transmission path has a memory cell MC, first and second bit lines BL and BLB, a bit line sensing amplifier BLSA, first and second segment data buses SIO and SIOB, first and second local data buses LIO and LIOB, a data bus sensing amplifier IOSA, and a global data bus GIO therein.
Herein, two NMOS transistors controlled by a bit line separation signal BISH are disposed between the first to second bit lines BL and BLB and the bit line sensing amplifier BLSA. Two PMOS transistors controlled by a column selection signal YI is disposed between the first to second segment data buses SIO, SIOB and the first to second local data buses LIO, LIOB. Two NMOS transistors controlled by an input/output switch control signal IOSW are disposed between the first to second segment data buses SIO, SIOB and the first to second local data buses LIO, LIOB.
FIG. 2B is an operation wave diagram of the circuit in FIG. 2A. Hereinafter, the read operation of the DRAM device is described referring to FIG. 2B.
When an active command is applied, a row address simultaneously applied with the active command is decoded to select a word line WL. Thus, the world line WL is activated. Accordingly, cell transistors in the memory cell MC connected to the activated word line WL are turned on. A cell capacitor, and first and second bit lines BL, BLB share charge. The first bit line BL and the second bit line BLB have a voltage difference due to the charge sharing.
The bit line sensing amplifier BLSA is enabled to sense the voltage difference between the first bit line BL and the second bit line BLB. Then, the bit line sensing amplifier BLSA amplifies the voltage difference up to pull-down power SB and pull-up power RTO levels. In FIG. 2B, the first bit line BL is amplified to a ground voltage ASS level and the second bit line BLB is amplified to a core voltage VCORE level.
Meanwhile, a read command is applied after a certain period of time tRCD from the active command application. A column address simultaneously applied with the read command is decoded to select one bit line. That is, the column selection signal YI corresponding to the selected bit line is activated. Two PMOS transistors controlled by the column selection signal YI are turned on. Thus, the first to second bit lines BL, BLB and the first to second segment data buses SIO, SIOB are connected to each other. As a result, the data on the first and second segment data buses SIO and SIOB are transmitted to the first and the second local data buses LIO and LIOB.
The input/output switch control signal IOSW is activated and the two NMOS transistors controlled by the input/output switch control signal IOSW are turned on. Thus, the data on the first and the second segment data buses SIO and SIOB is transmitted to the first and the second local data buses LIO and LIB.
Also, when a strobe signal IOSASTB generated by the read command is activated, the data bus sensing amplifier IOSA is enabled. Thus, the data bus sensing amplifier IOSA is enabled to sense and then amplify the data on the first and the second local data buses LIO and LIOB. The global data bus GIO is driven at a level corresponding to the sensed and amplified data.
The data amplified by the bit line sensing amplifier BLSA is re-stored in the memory cell MC before the bit line sensing amplifier BLSA is disabled. Thereafter, the first and the second bit lines BL and BLB are pre-charged.
The data bus sensing amplifier IOSA includes a sensing amplifying circuit for sensing and amplifying the data on the first and the second local data buses LIO and LIOB. The data bus sensing amplifier IOSA also includes a global data bus driving circuit for driving the global data bus GIO at a level corresponding to the sensed and amplified data.
FIG. 3A illustrates a sensing amplifying circuit disposed in the data bus sensing amplifier IOSA.
Referring to FIG. 3A, the data bus sensing amplifier IOSA includes a two-stage amplifying circuit. A first amplifying circuit 300A includes a current mirror type differential amplifier the mirrored parts of which are connected in parallel. The current mirror type differential amplifier is controlled by a first strobe signal IOSTB1. The first and the second local data buses LIO and LIOB are differential input terminals. A second amplifying circuit 300B includes a CMOS cross couple type differential amplifier. The CMOS cross couple type differential amplifier is controlled by a second strobe signal IOSTB2. The CMOS cross couple type differential amplifier receives first and second output signals D0 and D0B from the first amplifying circuit 300A.
FIG. 3B is an operation wave diagram of the sensing amplifying circuit in FIG. 3A.
When the input/output switch control signal IOSW is activated, the first and the second segment data buses SIO and SIOB are connected to the first and the second local data buses LIO and LIOB. Thus, an electric potential of the first and the second segment data buses SIO and SIOB is transmitted to the first and the second local data buses LIO and LIOB.
The first strobe signal IOSTB1 is activated after a certain period of time tA from the activation of the input/output switch control signal ISOW. The time tA is a margin time for developing the first and the second local data buses LIO and LIOB until the first amplifying circuit 300A has a sufficient voltage difference dV to sense the first and the second local data buses LIO and LIOB.
The second strobe signal IOSTB2 (or iostb2) is activated after a certain period of time tB from the activation of the first strobe signal IOSTB1. The tB is a margin time for the second amplifying circuit 300B.
The first and the second local data buses LIO and LIOB are pre-charged at a supply voltage VDD level. Likewise, first and second output terminals OUTNOD and OUTBNOD are pre-charged at the supply voltage VDD level.
FIG. 4 is a circuit diagram of a global data bus driving circuit in the data bus sensing amplifier IOSA.
Referring to FIG. 4, the global data driving circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a pull-up PMOS transistor MP1, and a pull-down NMOS transistor MN1. The first inverter INV1 receives a positive output signal OUT of the sensing amplifying circuit. The second inverter INV2 receives an output signal of the first inverter INV1. The third inverter INV3 receives a negative signal OUTB of the sensing amplifying circuit. The fourth inverter INV4 receives an output signal of the third inverter INV3. The fifth inverter INV5 receives an output signal of the fourth inverter INV4. The pull-up PMOS transistor MP1 has a source and a drain connected to the global data bus GIO and the second inverter INV2, respectively. The pull-up PMOS transistor MP1 receives an output signal of the second inverter INV2 as a gate input. The pull-down NMOS transistor NM1 has a source and a drain connected to a ground voltage terminal VSS and the global data bus GIO, respectively. The pull-down NMOS transistor NM1 receives an output signal of the fifth inverter INV5 as a gate input.
Recently, a highly integrated DRAM device employs a stack bank structure for reducing circuit dimensions by stacking more than two banks. When the stack bank structure is employed, a decoding circuit shares a plurality of banks. Thus, it is possible to reduce the entire decoding circuit dimensions.
FIG. 5 is a block diagram of a read path in a DRAM device with a stack bank structure.
Referring to FIG. 5, two banks are stacked in a column direction. That is, a second bank BANK1 is arranged over a first bank BANK0. A first local data bus LIO_UP corresponding to the second bank BANK1 is arranged to a global data bus GIO through the first bank BANK0. A second local data bus LIO_DN corresponding to the first bank BANK0 is arranged to the global data bus GIO.
First column controlling unit corresponding to the first bank BANK0 and second column controlling unit corresponding to the second bank BANK1 are arranged between the first bank BANK0 and the global data bus GIO. A write driver WD of FIG. 1 and the data bus sensing amplifier IOSA of FIG. 1 are employed in the first and the second column controlling units, respectively.
The invention relates to a data bus driving circuit in the data bus sensing amplifier IOSA. Thus, the description about the write driver WD is omitted.
In specific, the first column controlling unit includes the sensing amplifying circuit (FIG. 3A) for sensing and amplifying data on the second local data bus LIO_DN and the data bus driving circuit (FIG. 4). The second column controlling unit includes the sensing amplifying circuit for sensing and amplifying the data on the first local data bus LIO_UP and the data driving circuit.
In the typical the stack bank structure, each of the bank includes the data bus driving circuit in the column control block. Thus, dimensions of the column control block are large.